How to Use nRF54L15 Peripheral Power Domains to Minimize Idle Current

Cutting idle current on the nRF54L15 by managing peripheral power domains

You ported your nRF52 firmware to the nRF54L15, disabled every peripheral you weren’t using, and your idle current barely moved. The habits that worked on the nRF52/53 (flip the enable bit, trust the clock to gate) leave current on the table here, because the nRF54L15 has a knob those chips never had: it can collapse whole power domains.

Here’s the reset. The nRF52/53 gave you System ON/OFF plus per-peripheral clock control on top of a fairly monolithic power model. You disabled a peripheral, its clock stopped, and you saved a little leakage. The nRF54L15 groups peripherals into discrete power domains that can be independently unpowered. When a domain collapses, you stop paying for the leakage of every block inside it, not just the dynamic clock cost.

This article is about domain configuration and the µA you can expect, not how to measure it. I’ll flag every number as a datasheet typical or a bench estimate, and you should validate all of it on your own silicon before you commit to a battery budget.

The nRF54L15 Peripheral Power Domain Map

Think in two tiers. There’s always-on infrastructure (the RTC, GRTC, core retention, and wake logic) that has to stay alive to bring the chip back. Then there are collapsible peripheral domains that you power only when you need them.

+-----------------------------------------------------+
|                  Always-On Domain                   |
|     (RTC, GRTC, core retention, wake logic)         |
+-----------------------------------------------------+
        |              |                |
        v              v                v
+-------------+ +-------------+ +-------------------+
| Domain A    | | Domain B    | | Domain C          |
| (radio +    | | (serial:    | | (analog: SAADC,   |
|  assoc.)    | |  TWI/SPI/   | |  COMP, etc.)      |
|             | |  UARTE)     | |                   |
+-------------+ +-------------+ +-------------------+
  collapsible    collapsible      collapsible

The trap on the way in: power domains aren’t clock domains. On the nRF52/53 you got used to thinking about a peripheral’s state purely through its clock and its enable register. The nRF54L15 changes that. A clocked peripheral can sit inside a powered domain. Or it can be fully collapsed, so the silicon underneath it draws near-zero static current. Gating the clock cuts dynamic current. Collapsing the domain cuts the leakage floor. You want both, but the second one is where the nRF54L15 pulls ahead.

Map your application’s peripherals onto these domains early. A design that touches one SPI bus and one ADC channel ideally keeps the radio domain and serial domain collapsed between bursts, and treats the analog domain the same way. If you can draw that timeline before you write firmware, the config steps below mostly fall out of it.

Quick Win #1: Collapse Unused Serial Domains

This is the highest-frequency win because almost every design has a TWI, SPI, or UARTE instance it doesn’t use, or uses only in short bursts.

On the nRF52/53, an unused SPI you’d simply leave disabled. The block still sits in a powered region and contributes a small static leakage you can’t really claw back. On the nRF54L15, leaving the peripheral disabled isn’t the same as leaving its domain collapsed. If nothing else in that domain is active, you want the domain unpowered.

In practice you don’t touch the power domain register directly. The serial peripheral’s uninit path drives it. With the Hubble Device SDK or a plain Zephyr build, calling the nrfx uninit (for example nrfx_spim_uninit()) or letting Zephyr’s device PM put the instance into PM_DEVICE_STATE_SUSPENDED releases the domain when no other peripheral holds it up. Verify the exact symbol and PM behavior against your nRF Connect SDK version (as of February 2025 the device PM hooks for the L-series serial drivers were still settling, so check release notes).

Scenario                    | nRF52/53 idle | nRF54L15 idle
----------------------------|---------------|---------------
Unused SPI, peripheral off  |   ~1.5 µA     |   ~1.2 µA      [VERIFY: datasheet typ.]
Domain collapsed            |   n/a         |   ~0.4 µA      [bench estimate]

The gap between “disabled” and “collapsed” is the point. On the nRF52/53 there’s no third row, you’ve already done everything you can. The collapsed figure here is my bench estimate pending the measurement piece, so treat it as directional, not gospel.

One caveat: shared pins and shared resources can hold a domain up even when you think you’ve released it. If your collapsed-domain current doesn’t drop, look for another driver in the same domain that’s still initialized.

Quick Win #2: Analog Domain Management

The nRF52/53 habit that hurts you here: leaving analog supervision running because periodic sampling felt cheap. A COMP watching a threshold, or a SAADC left initialized between reads, keeps the analog domain powered the entire idle window.

If your application only needs periodic samples, collapse the analog domain between them. The pattern is: wake on the RTC/GRTC, power the analog domain, run the SAADC conversion, uninit, let the domain collapse, sleep. You pay a wake cost each cycle (the domain needs time to power up and the reference to settle), so this trades a small per-sample energy bump for a much lower idle floor.

The math is duty-cycle dependent. Holding the analog domain up continuously might cost a few µA of continuous draw [VERIFY: datasheet typ.]. Collapse it between samples and you drop toward the leakage floor of the rest of the chip, paying only the wake-and-settle energy at your sample rate. At a 1 Hz sample rate the collapsed approach wins comfortably. At a few kHz the wake cost starts eating the saving (more on that threshold next).

For the SAADC, drive this through the nrfx uninit or Zephyr device PM rather than poking the domain control directly. Confirm the settle timing in the nRF54L15 product spec for your reference selection; internal references settle faster than external.

Quick Win #3: Retention vs. Re-Init Tradeoffs

Collapsing a domain throws away the peripheral’s configuration state. Bring it back and you re-init: re-write registers, re-load calibration, wait for settle. That re-init costs energy and time, and there’s a crossover where it eats the idle saving you were chasing.

Rule of thumb: if the sleep window between uses is long relative to the re-init cost, collapse the domain. If you’re cycling fast, keep it powered and just gate the clock. Collapsing tends to win when your sleep window runs past ~10 ms and you wake fewer than a few hundred times a second. Below that, the re-init overhead usually dominates and you should keep state resident.

This is where nRF52/53 instincts mislead you. On those chips there was no “collapse” decision to make, so you never had to weigh re-init against retention. Profile both paths on real hardware. Calibration-heavy peripherals (the SAADC again) carry the highest re-init cost, so they’re the most sensitive to this threshold.

Putting It Together: A Worst-Case nRF54 Idle Current Budget

Stack the three wins on a representative design: a sensor node with one SPI bus, one SAADC channel, the radio idle between transmits, and a 1 Hz wake cadence.

Baseline (naive port)        ............ 12.0 µA   [bench estimate]
- collapse serial domains    ............ -0.8 µA
- analog collapse            ............ -2.5 µA
- retention tuning           ............ -0.6 µA
                             ====================
Optimized idle               ............  8.1 µA   [bench estimate]

These are bench estimates anchored to nRF54L15 product spec typical figures, and bracketed where the spec didn’t give me a number. The pattern is what matters: the analog collapse is usually your biggest single lever for a sampling design, the serial domains are easy free money, and retention tuning is the fine adjustment once the big rocks are placed. A naive nRF52/53-style port that only disables peripherals leaves most of that delta unclaimed, because it never collapses anything.

The floor you can reach is set by which domains you let stay powered, not by how aggressively you gate clocks.

Where to Go Next

Every µA figure here is either a datasheet typical or my bench estimate, so the next step is to put a PPK2 on your own board and confirm the deltas under your real duty cycle. I’ll walk through that measurement workflow for the nRF54 in a follow-up piece. Wire up the domain config above first, then measure, because the collapse-versus-gate decisions only prove out on silicon under your exact wake pattern.

Feedback notes (flagged for review):

  • All µA figures are placeholders/estimates. Before publishing, replace bracketed [VERIFY: datasheet typ.] and [bench estimate] values with verified numbers from the nRF54L15 Product Specification or a real PPK2 capture. Several are plausible-but-unconfirmed and could reflect poorly if a reader benchmarks against them and finds them off.
  • The nrfx_spim_uninit() symbol and the device PM state behavior need a hard check against the current nRF Connect SDK; the “February 2025” caveat is a placeholder and must be updated to the real publish-date SDK version.
  • Domain-to-peripheral mapping in the diagram is illustrative. Confirm against the datasheet’s actual power domain partitioning before publish; if the real partitioning differs, the whole “collapse unused serial domains” framing needs adjusting.
  • Internal links requested in the brief (pillar page, nRF52/53 patterns, Zephyr PM on Nordic) weren’t available in the provided docs list, so only the SDK GitHub link is included. Add the others once URLs exist.

Hubble Network brings satellite connectivity directly to BLE devices like the nRF54L15, extending low-power designs to global reach without added gateways or infrastructure. See how it works →