10 Common Mistakes on Your First Custom PCB
You open the padded envelope from the fab house. Five matte-green boards, your name on the silkscreen, the smell of solder mask. You plug one in. Nothing. Or worse: a faint hiss, then a wisp of smoke from a 6 mil trace that was supposed to carry 2 amps.
Welcome to your first custom PCB.
Most first-board failures aren’t exotic. They cluster around a predictable set of mistakes that breadboard intuition doesn’t prepare you for. On a breadboard, traces are zero-ohm wires, ground is ground, and parts always fit. On copper, none of that’s true.
Here are the 10 mistakes we see over and over, organized across the design lifecycle. We help hardware teams ship connected devices, and the same patterns show up whether someone’s building a smart sensor or their first dev board.
SCHEMATIC ──► LAYOUT ──► DFM ──► VERIFY ──► [FAB]
(1,2,3) (4,5,6,7) (8,9) (10)Schematic-Stage Mistakes
1. Wrong or unverified footprints
You drag a part from a vendor library, wire it up, and assume the footprint is correct. It usually isn’t. Pin pitch off by 0.1mm, pad sizes too small for hand soldering, or pin numbering mirrored because the symbol matches the top view but the footprint matches the bottom.
Why it happens: Vendor library parts often aren’t as authoritative as they look.
What it costs: Dead boards. Tombstoned 0402s. A QFN you can’t reflow because the thermal pad is wrong. Full respin: $200 and 2 weeks.
The fix: Open the datasheet. Compare the recommended land pattern (IPC-7351 if the vendor provides it) against your footprint. Every pin, every pad, every time. Print the footprint at 1:1 and lay the actual part on top.
2. Missing or misplaced decoupling capacitors
Every IC’s power pin gets a 100nF cap. You knew that. But you put them in a neat row at the edge of the board because it looked tidy.
Why it happens: Schematics treat decoupling as a checkbox. Layout treats it as decoration.
What it costs: Brown-outs on transients, MCU resets under load, noise on ADC readings, RF emissions that fail compliance. The board “kind of works.”
The fix: Place the cap within 5mm of the power pin, on the same layer if possible, with a short via to ground. Capture placement intent in the schematic with a note: “C7 within 5mm of U2 pin 14.”
BAD: GOOD:
[IC]......[C] [IC][C]
long trace adjacent3. No power budget
You spec a 150mA LDO. The MCU pulls 40mA, the radio pulls 80mA at peak, the sensor pulls 20mA, and you have 8 LEDs. You discover this halfway through layout.
Why it happens: Breadboard supplies are infinite. Your bench PSU never complained.
What it costs: A regulator swap means new footprint, new thermal pad, new layout. Sometimes a new schematic page if you need to add a buck converter.
The fix: Build a power budget spreadsheet before you place a single component. Worst-case current per rail, with 50% margin. If you can’t justify the regulator on paper, you can’t justify it in copper.
Layout-Stage Mistakes
4. Default trace widths everywhere
The EDA tool’s default is 10 mil. You route the entire board at 10 mil, including the rail feeding a 2A motor driver.
Why it happens: The DRC doesn’t yell at you for under-sized power traces unless you’ve configured it to.
What it costs: Voltage drop, copper heating, and in extreme cases a trace that lifts off the substrate. Sometimes the board works at room temp and fails at 50°C.
The fix: Use this as a starting point, then verify with an IPC-2152 calculator:
CURRENT MIN TRACE WIDTH (1oz Cu, external)
0.5 A ~10 mil
1.0 A ~20 mil
2.0 A ~40 mil
3.0 A ~60 milDefine net classes for power, signal, and high-current. Set widths per class.
5. Poor grounding strategy
Daisy-chained ground returns. A split plane under a high-speed signal. A ground pour that’s actually 12 disconnected islands separated by traces.
Why it happens: Ground feels like a single node because the schematic shows it that way. Copper has impedance, schematics don’t.
What it costs: Ground bounce, EMI failures, mystery glitches that only happen when the radio transmits. The kind of bug you’ll spend a weekend probing with a scope.
The fix: Continuous ground pour on at least one layer. Stitch with vias. Don’t route signals across plane splits. If you’re mixing analog and digital, read Henry Ott’s Electromagnetic Compatibility Engineering before you split anything; partitioning ground is a tool, not a default.
6. Placement driven by aesthetics
The crystal looks nice over there, 30mm from the MCU. The hot LDO is right next to the precision op-amp because they fit. The USB connector is in the middle of the board because the layout was symmetric.
Why it happens: You’re optimizing for what looks clean in the 2D viewer. Signal flow and thermals don’t show up there.
What it costs: Crystals that don’t start. Analog readings that drift with regulator temperature. Connectors that fight your enclosure.
The fix: Place by function, then route. Crystals within 10mm of the MCU with a guard ring. Heat sources away from temperature-sensitive parts. Connectors on board edges.
7. Forgetting mechanical constraints
The board is 50x40mm. The enclosure cavity is 48x40mm. The mounting holes are M3 in your CAD and M2.5 in your layout. The USB-C connector overhangs the board edge by 1.2mm and won’t clear the enclosure wall.
Why it happens: Mechanical and electrical live in different files, often different tools, often different people.
What it costs: A board that works electrically but can’t be installed. New revision, new fab order, new 2 weeks.
The fix: Import the enclosure DXF or STEP into your EDA tool. Lock the board outline and mounting holes before placing components. Verify connector cutouts against the enclosure CAD.
DFM and Fab-Ready Mistakes
8. Ignoring DRC errors or running with loose rules
You have 47 DRC warnings. You silence them because “they’re just warnings.” Or your clearances are set to 4 mil because that’s what the tool defaulted to, but your fab house’s standard process is 6 mil.
Why it happens: DRC feels like bureaucracy, but it’s manufacturing tolerance encoded as constraints.
What it costs: Shorts between traces. Solder bridges. The fab house quietly bumping you to a more expensive process, or rejecting the order. Common PCB DRC errors (acid traps, slivers, insufficient annular ring) become real defects in copper.
The fix: Download your fab house’s capability sheet. Configure DRC to match: clearance, minimum trace, minimum drill, annular ring. Resolve every error.
9. Silkscreen and assembly oversights
No pin-1 indicator on the QFN, no polarity mark on the electrolytic, reference designators hidden under components so the assembler can’t tell R12 from R13, no board version number so you can’t tell rev A from rev B six months later. Silkscreen feels cosmetic, but it’s documentation for the human (you, in 3 months) who has to debug, rework, or assemble. The fix: pin 1 dots on every IC, polarity on every diode and electrolytic, reference designators visible after assembly, version number and date in the corner. Your initials, if you’re brave.
Verification-Stage Mistake
10. Skipping the pre-fab review
You finish layout at 11pm, run DRC, and click “generate Gerbers.” 30 seconds later you’ve uploaded to the fab house.
Why it happens: Excitement. The finish line feels close.
What it costs: Everything above, multiplied. The 30 minutes you didn’t spend reviewing becomes 2 weeks of respin.
The fix: Walk away for a day. Open the Gerbers in an external viewer (not your EDA tool’s preview, an actual Gerber viewer). Run the checklist below. Get a second pair of eyes if you can; if you can’t, your future self at 9am tomorrow counts.
The Pre-Fab Review Checklist
PRE-FAB REVIEW CHECKLIST
[ ] Every footprint verified against datasheet
[ ] Decoupling caps placed within 5mm of every IC power pin
[ ] Power rails sized for worst-case current + 50% margin
[ ] Trace widths match current (use a calculator)
[ ] Continuous ground pour; no splits under fast signals
[ ] Crystals/oscillators within 10mm of MCU
[ ] Mounting holes match enclosure CAD
[ ] DRC passes with fab-house rules (not defaults)
[ ] Silkscreen: pin 1, polarity, version, your initials
[ ] Gerbers viewed in external viewer before submissionCopy it. Tape it to your monitor. 30 minutes of review beats 2 weeks of respin.
Treating the First Board as a Learning Artifact
Your first PCB will have mistakes. The goal is catching the expensive ones before fab and accepting the cheap ones after. The cheap ones (a missing test point, a slightly tight clearance you got away with) teach you faster than any tutorial. The expensive ones (wrong footprint, no decoupling, undersized rail) eat weeks.
If you’re building a connected device and want a head start on the radio side, our terrestrial device integration guide covers the layout and antenna decisions that tend to bite people on rev A. And the reference Zephyr application shows what a working firmware/hardware combination looks like, which is useful when you’re trying to figure out whether your bug is in copper or code.
Either way: print the checklist. Run it before every fab order. Your future self will thank you.
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